Plasma displays with a wide screen format are being widely adopted as the next generation displays, namely replacing the old Brownian tube technology. An alternating-current-type (AC) plasma display, which has been used mainly, feeds discharge sustaining pulse voltages alternately to panel electrodes to display images. The three-electrodes surface-discharge structure employed for the plasma displays includes a sustain electrode for display discharge, a scan electrode for display discharge, and an address electrode for write discharge. The scan and address electrodes activate write discharge therebetween. The scan and sustain electrodes activate surface discharge for displaying therebetween.
A data driver integrated circuit (IC) is connected to the address electrode, a scan driver IC to the scan electrode, and a sustain driver circuit to the sustain electrode. Since the power supply voltage of around 140 V is applied to the scan driver IC and a power supply voltage of around 200 V to the sustain driver circuit, it is necessary for a 42 inch display, for example, to generate the maximum instantaneous current of around 300 A in total flow therein. The maximum instantaneous current mainly contains gas discharge current. The maximum load occurs when the gas discharge current flows. A light load occurs when the capacitive electric charges from the panel electrode potential change flow. Therefore, it is important to precisely operate the scan driver IC and the sustain driver circuit.
In the following descriptions, the voltages do not represent the absolute potentials but the potential differences applied in the operating states of the constituent devices. Referring to FIG. 7, which is a block circuit diagram of a conventional scan driver IC, the conventional scan driver IC includes two n-channel insulated gate bipolar transistors (IGBTs: hereinafter referred to as “NOH and NOL”, respectively) 101 and 102 working as output devices, each exhibiting a high breakdown voltage. The NOH and NOL transistors 101,102 are connected in series between a high-potential power supply terminal (hereinafter referred to as a “VDH”) 103 and a ground terminal (hereinafter referred to as “GND”) 104, constituting a totem pole output circuit that feeds a bias voltage from a high-potential power supply to the high-side device (NOH 101). The gate terminal of the NOH transistor 101 is connected to the connection point of a p-channel MOSFET (hereinafter referred to as a “PD”) 105 and an n-channel MOSFET (hereinafter referred to as an “ND”) 106, both constituting a driver circuit. The gate terminal of the NOL transistor 102 is connected to a driver circuit, configured in a control signal generating section 109 incorporating a timer circuit therein, to change the potential of an output terminal (hereinafter referred to as a “DO”) 110. The control signal generating section 109 is disposed, assuming the short circuit of the inverter output (DO) 110 with the power supply, for lowering the gate voltages of the NOH and NOL transistors 101,102 to prevent the IC from being broken down when the next clock signal is not input to the control signal generating section 109 within a certain period after the last clock signal is input thereto.
Referring to FIG. 8, which is an equivalent circuit diagram of a conventional sustain driver circuit, the conventional sustain driver circuit includes an n-channel IGBT (hereinafter referred to as an “NOH”) 111, which is an output device on the high side, and an n-channel IGBT (hereinafter referred to as an “NOL”) 112, which is an output device on the low side. The NOH and NOL transistors 111, 112 are connected in series between an external high-potential power supply terminal and a ground terminal, constituting a totem pole output circuit based on the so-called boot-strap system. The gate terminals of the NOH and NOL transistors 111, 112 are connected to the respective driver circuits, each including a p-channel MOSFET and an n-channel MOSFET connected in series.
For improving the reliability, a control circuit has been proposed for preventing an over voltage in the high-side control power supply voltage, for preventing the output devices from malfunctioning, and for preventing breakdown of the output devices. See Unexamined Japanese Patent Application 2005-175454, which corresponds to USPGP 2005/0134533, for example. For protection against an over voltage and for size and costs reduction, the control circuit described above utilizes a bipolar transistor circuit to clamp the control power supply voltage.
Referring to FIG. 9, which illustrates a fundamental block circuit diagram of a conventional driver circuit, the conventional driver circuit will be described below. The drain terminals of a p-channel MOSFET (PD) 121 exhibiting a low breakdown voltage and an n-channel MOSFET (ND) 122 exhibiting a low breakdown voltage are connected to each other. The source terminal of the PD 121 is connected to the positive electrode of a control power supply (hereinafter referred to as a “VDD”) 123 and the source terminal of the ND 122 to the negative electrode of the VDD 123. The gate terminals of the PD 121 and the ND 122 are connected to each other and to an input terminal. The emitter terminal of an n-channel IGBT (hereinafter referred to as an “NO”) 124, which is an output device exhibiting a high breakdown voltage, is connected to the negative electrode of the VDD 123. The gate terminal of the NO 124 is connected to the drain terminals of the PD 121 and the ND 122 via a resistor (hereinafter referred to as an “R”) 125. The collector terminal, which is an output terminal, of the NO 124 is connected, for example, to a load. Alternatively, an n-channel MOSFET or an NPN transistor can be substituted for the NO 124. Depending on the circuit characteristics, R 125 may be unnecessary.
When the input terminal is biased at a high level (hereinafter referred to as a “Hi-level”: the positive potential of VDD 123) in the driver circuit as described above, the PD 121 is ON and the ND 122 is OFF, biasing the drain terminals thereof at a low level (hereinafter referred to as a “Lo-level”: the negative potential of VDD 123). Since the gate potential of the NO 124 connected to the drain terminals of the PD 121 and the ND 122 is at the Lo-level, the NO 124 is brought into the OFF-state. By connecting the output terminal of the NO 124 in the OFF-state to the high potential side of a high-voltage circuit disposed separately and by connecting the negative electrode of VDD 123 to the low potential side of the high-voltage circuit, a desired high voltage is applied between the collector and emitter of the NO 124. Since the gate potential of the NO 124 is set at the Hi-level as the input terminal potential is changed over to the Lo-level and the NO 124 is brought into the ON-state, so that current flows from the high-voltage circuit into the collector of the NO 124 and returns to the high-voltage circuit from the emitter of the NO 124.
When the main current flows as described above, the output terminal voltage of the NO 124 will lower, if no anomaly, such as a terminal short-circuit, occurs. As the output terminal voltage of the NO 124 lowers, the current, caused by discharging the electric charges in the feedback capacitance between the collector and gate of the NO 124, flows from the collector of the NO 124 to the gate of the NO 124 via the high-voltage circuit (including the output device), the negative electrode of the VDD 123, the positive electrode of the VDD 123, and the PD 121. The current raises the voltage of the VDD 123.
In the usual circuit design, the PD 121 is provided with a current feed ability enough to complete the charging of the gate of the NO 124 within a predetermined time, and the R 125 is set such that the R 125 relaxes the current fed by the PD 121 and the current flowing into the NO 124 from the feedback capacitance. The voltage of the VDD 123 is set to flow the gas discharge current in the plasma display panel with low resistance. Since the conventional driver circuit drives the gate of the NO 124 at the same voltage as the voltage under the maximum load even with the light load as previously described, vigorous output voltage variations occur, as well as noise occurring, via the feedback capacitance of the NO 124, further causing an over voltage on the VDD 123. However, the countermeasures described in the aforementioned published patent applications cannot solve the above-described problems drastically.
In the method that lowers the output device gate voltage, if the next clock signal is not input within a predetermined period of time after the last clock signal input, to prevent the IC from breaking down, sufficient gas discharge current cannot flow after lowering the gate voltage. Therefore, the above-described method has limitations on driving the plasma display panel. To solve the problems described above, a more complicated circuit configuration has been proposed. However, it is difficult to employ such complicated circuit configuration for the usual circuit since it increases the cost and creates problems associated with higher circuit integration.
Accordingly, there remains a need for a semiconductor circuit that provides over voltage protection without complicating the configuration thereof. The present invention addresses this need.